In order to conserve energy and reduce thermal load, many processors include the option of operating in several operating states. During the times when the processor is operating, the greatest processor clock frequency that is available may be selected to enhance processor throughput. However, during the times when instructions are not being processed, the processor may transfer to one of several available low-power states. In these states, the processor clock frequency may be reduced or completely stopped, but cache-coherency snooping may be permitted. In other states, enough of the processor may be powered-down that cache-coherency snooping may not be permitted, and the operating system software must provide for cache coherency. In the Pentium® class processors produced by Intel® Corporation, the normal operation state may be called the C0 state, the low-power states may be called the C1, C2, C3, and C4 states.
The existing low-power C1 and C2 states are not optimal with regards power conservation. The C3 and C4 states achieve higher levels of power conservation, but have several drawbacks that limit their use. One is the inability to participate in cache-coherency snoop operations. This could mean that they cannot be used when certain “bus mastering” peripherals are attached. Such bus mastering peripherals using such connections as universal serial bus (USB) and other quick-connection interfaces are becoming increasing common. Another problem is that the low-power states may have long exit latencies (the time required to come out of the low-power states). Therefore none of these existing low-power are optimal for future processor products.